? semiconductor components industries, llc, 2002 january, 2002 rev. 6 1 publication order number: mc100lvep210/d mc100lvep210 2.5v / 3.3v1:5 dual differential ecl/pecl/hstl clock driver the mc100lvep210 is a low skew 1to5 dual differential driver, designed with clock distribution in mind. the ecl/pecl input signals can be either differential or singleended if the v bb output is used. the signal is fanned out to 5 identical differential outputs. hstl inputs can be used when the ep210 is operating in pecl mode. the lvep210 specifically guarantees low outputtooutput skew. optimal design, layout, and processing minimize skew within a device and from device to device. to ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 w even if only one output is being used. if an output pair is unused, both outputs may be left open (unterminated) without affecting skew. the mc100lvep210, as with most other ecl devices, can be operated from a positive v cc supply in pecl mode. this allows the lvep210 to be used for high performance clock distribution in +3.3 v or +2.5 v systems. singleended clk input operation is limited to a v cc 3.0 v in pecl mode, or v ee 3.0 v in ecl mode. designers can take advantage of the lvep210's performance to distribute low skew clocks across the backplane or the board. in a pecl environment, series or thevenin line terminations are typically used as they require no additional power supplies. for more information on using pecl, designers should refer to application note an1406/d. ? 85 ps typical devic etodevice skew ? 20 ps typical outputtooutput skew ? v bb output ? jitter less than 1 ps rms ? 350 ps typical propagation delay ? maximum frequency > 3 ghz typical ? the 100 series contains temperature compensation ? pecl and hstl mode operating range: v cc = 2.375 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 2.375 v to 3.8 v ? open input default state ? lvds input compatible ? fully compatible with motorola mc100ep210 32 1 http://onsemi.com 32lead lqfp fa suffix case 873a marking diagram* mc100 awlyyww a = assembly location wl = wafer lot yy = year ww = work week *for additional information, see application note and8002/d lvep210 device package shipping ordering information mc100lvep210fa lqfp 250 units/tray mc100lvep210far2 lqfp 2000 tape & reel
mc100lvep210 http://onsemi.com 2 clkn*, clkn ** ecl/pecl/hstl clk inputs v bb reference voltage output v cc 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 qb4 qb4 qb3 qb3 qb2 qb2 v cc v cc qa0 qa0 qa1 qa1 qa2 qa2 v cc v ee v bb v cc qb1 qb1 qb0 qb0 qa4 qa4 qa3 qa3 qa0 qa0 qa1 qa1 qa2 qa2 qa3 qa3 qa4 qa4 v bb clka clka nc qb0 qb0 qb1 qb1 qb2 qb2 qb3 qb3 qb4 qb4 clkb clkb warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. pin description pin qn0:4, qn0:4 ecl/pecl outputs function v cc positive supply v ee negative supply figure 1. 32lead lqfp pinout (top view) figure 2. logic diagram * pins will default low when left open. ** pins will default to v cc /2 when left open. mc100lvep210 clka clka clkb clkb v ee v cc attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity (note 1) level 2 flammability rating oxygen index ul94 code v0 a 1/8 28 to 34 transistor count 461 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
mc100lvep210 http://onsemi.com 3 maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v 6 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6 6 v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junctiontoambient) 0 lfpm 500 lfpm 32 lqfp 32 lqfp 80 55 c/w c/w q jc thermal resistance (junctiontocase) std bd 32 lqfp 12 to 17 c/w t sol wave solder < 2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur. pecl dc characteristics v cc = 3.3 v; v ee = 0 v (note 3) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 60 70 90 60 70 90 60 70 90 ma v oh output high voltage (note 4) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 4) 1355 1480 1695 1355 1480 1695 1355 1480 1695 mv v ih input high voltage (singleended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (singleended) 1490 1675 1490 1675 1490 1675 mv v bb output reference voltage (note 5) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential) (note 6) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current 150 150 150 m a i il input low current clk clk 0.5 150 0.5 150 0.5 150 m a note: 100lvep circuits are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been e stablished. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintain ed. 3. input and output parameters vary 1:1 with v cc . v ee can vary + 0.925 v to 0.5 v. 4. all loading with 50 w to v cc 2.0 volts. 5. single ended input operation is limited v cc 3.0 v in pecl mode. 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc100lvep210 http://onsemi.com 4 pecl dc characteristics v cc = 2.5 v; v ee = 0 v (note 7) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 60 70 90 60 70 90 60 70 90 ma v oh output high voltage (note 8) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ol output low voltage (note 8) 555 680 895 555 680 895 555 680 895 mv v ihcmr input high voltage common mode range (differential) (note 9) 1.2 2.5 1.2 2.5 1.2 2.5 v i ih input high current 150 150 150 m a i il input low current clk clk 0.5 150 0.5 150 0.5 150 m a note: 100lvep circuits are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been e stablished. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintain ed. 7. input and output parameters vary 1:1 with v cc .. v ee can vary + 0.125 v to 1.3 v. 8. all loading with 50 w to v ee . 9. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. necl dc characteristics v cc = 0 v, v ee = 2.375 v to 3.8 v (note 10) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 60 70 90 60 70 90 60 70 90 ma v oh output high voltage (note 11) 1145 1020 895 1145 1020 895 1145 1020 895 mv v ol output low voltage (note 11) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv v ih input high voltage (singleended) 1165 880 1165 880 1165 880 mv v il input low voltage (singleended) 1810 1625 1810 1625 1810 1625 mv v bb output reference voltage (note 12) 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage common mode range (differential) (note 13) v ee + 1.2 0.0 v ee + 1.2 0.0 v ee + 1.2 0.0 v i ih input high current 150 150 150 m a i il input low current clk clk 0.5 150 0.5 150 0.5 150 150 m a note: 100lvep circuits are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been e stablished. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintain ed. 10. input and output parameters vary 1:1 with v cc . 11. all loading with 50 w to v cc 2.0 volts. 12. single ended input operation is limited v ee 3.0v in necl mode. 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. hstl dc characteristics v cc = 2.375 to 3.8 v, v ee = 0 v 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v ih input high voltage 1200 1200 1200 mv v il input low voltage 400 400 400 mv v input crossover voltage 680 900 680 900 680 900 mv i cc power supply current 60 70 90 60 70 90 60 70 90 ma
mc100lvep210 http://onsemi.com 5 ac characteristics v cc = 0 v; v ee = 2.375 to 3.8 v or v cc = 2.375 to 3.8 v; v ee = 0 v (note 14) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f maxpecl/ hstl maximum frequency (see figure 3. f max /jitter) > 3 > 3 > 3 ghz t plh t phl propagation delay propagation delay @ 2.5 v 220 300 380 270 350 430 300 330 500 410 750 490 ps t skew withindevice skew (note 15) devicetodevice skew (note 16) 20 85 25 160 20 85 25 160 20 85 35 160 ps t jitter cycletocycle jitter (see figure 3. f max /jitter) 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp minimum input swing 150 800 1200 150 800 1200 150 800 1200 mv t r /t f output rise/fall time (20%80%) 100 170 250 120 190 270 150 280 350 ps 14. measured with 750 mv source, 50% duty cycle clock source. all loading with 50 w to v cc 2 v. 15. skew is measured between outputs under identical transitions of similar paths through a device. 16. devicetodevice skew for identical transitions at identical v cc levels. 0 100 200 300 400 500 600 700 800 0 1000 2000 3000 4000 5000 6000 figure 3. f max /jitter frequency (mhz) 1 2 3 4 5 6 7 8 (jitter) v outpp (mv) jitter out ps (rms) driver device receiver device d d q q 50 w 50 w v tt v tt = v cc 2.0 v figure 4. typical termination for output driver and device evaluation (refer to application note and8020 termination of ecl logic devices.)
mc100lvep210 http://onsemi.com 6 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8009 eclinps plus spice i/o model kit and8020 termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
mc100lvep210 http://onsemi.com 7 package dimensions lqfp fa suffix 32lead plastic package case 873a02 issue a detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section aeae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 t z u t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ac ab m 8x t, u, z t-u m 0.20 (0.008) z ac dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction.
mc100lvep210 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100lvep210/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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